As data communication technologies have developed, rapid graphics processing capabilities have become more important for electronic products. For efficiency of a memory device, only a relatively small amount of data requiring high-speed processing is stored in a graphics memory, and most of the data is stored in a main memory. One high-speed data processing technique is to increase I/O bandwidth.
Recently, multi-chip package (MCP) technologies have been used to achieve high storage densities. For example, an MCP technology may implement a memory device having a 64-bit architecture using two memory chips having a 32-bit architecture.
Conventionally, two individual unit memory chips may be mounted on one package frame, and pads where an identical signal is provided to the two individual unit memory chips from an external device may be wire-bonded to each other.
Korean Patent No. 10-0422469 discloses a memory device capable of controlling storage density by packaging two or more non-separate unit memory chips formed on a wafer as a group. The memory device disclosed in Korean Patent No. 10-0422469 does not cut a scribe line between the unit memory chips but uses the scribe line as a connection path between the unit memory chips. The disclosure of Korean Patent No. 10-0422469 is hereby incorporated herein in its entirety by reference.